VHDL实现194功能代码

 完整代码：

LIBRARY IEEE;                                                            USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY jicunqi ISPORT(CR,CP,SL,SR:IN STD_LOGIC;S0,S1:IN STD_LOGIC;D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q0,Q1,Q2,Q3:out STD_LOGIC);END jicunqi;ARCHITECTURE behavior OF jicunqi ISsignal M1:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CR,CP)BEGINIF CR='0'     THENM1<="0000";ELSIF CP'EVENT AND CP ='1'    THENIF S1='0'     AND S0='1' THEN    M1<=SR&M1(3 DOWNTO 1);ELSIF S1='1' AND S0='0'     THEN M1<=M1(2 DOWNTO 0)&SL;ELSIF S1='1' AND S0='1'     THEN M1<=D;END IF;END IF;END PROCESS;Q3<=M1(0);Q2<=M1(1);Q1<=M1(2);Q0<=M1(3);END BEHAVIOR;