FPGA沿信号检测程序

1 程序代码

module remote_rcv(input                  sys_clk   ,  //系统时钟input                  sys_rst_n ,  //系统复位信号，低电平有效input                  PULSE        // 输入脉冲);reg r0;  
reg r1;
reg pos_remote_in;
reg neg_remote_in;assign  pos_remote_in = (~r1) & r0;//上升沿
assign  neg_remote_in = r1 & (~r0);//下降沿always @(posedge sys_clk or negedge sys_rst_n) beginif(!sys_rst_n) beginr0 <= 1'b0;r1 <= 1'b0;endelse beginr0 <= PULSE;r1 <= r0;end
endendmodule

时序图