VHDL——锁存器

1.端口图

2.VHDL语言

library ieee;
use ieee.std_logic_1164.all;entity latch1 is
port( d : in std_logic ;q : out std_logic;ena : in std_logic);
end latch1;architecture example of latch1 is
signal sig_save : std_logic := '0' ; 
beginprocess(d,ena)beginif ena = '1' then sig_save <= d ;end if ;q <= sig_save ;end process;
end example;